Samsung begins chip production using 3nm process technology with GAA architecture

Optimized 3nm process provides 45% less power consumption, 23% better performance and 16% smaller surface area compared to 5nm process

The leaders of Samsung Foundry Business and Semiconductor R&D Center hold up three fingers to symbolize 3nm, celebrating the company’s first-ever production of the 3nm process using GAA architecture.

Samsung Electronics the world leader in semiconductor technology, today announced that it has begun production of its 3-nanometer (nm) process node using Gate-All-Around (GAA) transistor architecture.

Multi-Bridge Channel FET (MBCFET), Samsung’s GAA technology implemented for the first time ever defies the performance limitations of FinFET, improving energy efficiency by lowering the power supply voltage level, while also improving performance by increasing the drive current capacity.

Samsung is launching the first application of the nanosheet-transistor with semiconductor chips for high-performance, energy-efficient computing applications and plans to expand to mobile processors.

“Samsung has grown rapidly as we continue to show leadership in applying next-generation technologies to manufacturing, such as FinFET, the foundry industry’s first High-K Metal Gate, and EUV. We aim to continue this leadership with the world’s first 3nm process with the MBCFET,” said dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics. “We will continue active innovation in competitive technology development and build processes that help accelerate technology maturity attainment.”

(Left to right) Michael Jeong, Corporate Vice President; Ja-Hum Ku, Corporate Executive Vice President; and Sang Bom Kang, Corporate Vice President at Samsung Foundry Business hold up 3nm wafers on the production line of Samsung Electronics Hwaseong Campus.

Design-Technology Optimization for Maximized PPA

Samsung’s proprietary technology uses nanosheets with wider channels, enabling higher performance and greater energy efficiency compared to GAA technologies that use nanowires with narrower channels. Using the 3nm GAA technology, Samsung can adjust the channel width of the nanosheet to optimize power consumption and performance to meet different customer needs.

In addition, the design flexibility of GAA is very beneficial for Design Technology Co-Optimization (DTCO),1 which helps increase the benefits of Power, Performance, Area (PPA). Compared to the 5nm process, the 3nm process of the first generation can reduce power consumption by up to 45%, improve performance by 23% and reduce the surface area by 16% compared to 5nm, while the 3nm process of the second generation improves power consumption by up to 50%, improves performance by 30% and reduces surface area by 35%.

Delivering 3nm design infrastructure and services with SAFE Partners

As technology nodes shrink and chip performance needs grow, IC designers face the challenge of processing massive amounts of data to verify complex products with more features and tighter scalability. To meet such demands, Samsung is pursuing a more stable design environment to reduce the time required for the design, verification and sign-off process, while increasing product reliability.

Since the third quarter of 2021, Samsung Electronics has delivered proven design infrastructure through extensive preparation with Samsung Advanced Foundry Ecosystem (SAFE) partners, including Ansys, Cadence, Siemens and Synopsys, to help customers perfect their product in less time.

Quotes from SAFE Partners

  • AnsysJohn Lee, Vice President and General Manager of the Electronics, Semiconductor & Optics Business Unit at Ansys
    “Together, Ansys and Samsung continue to deliver technology for the most advanced designs, now at 3nm with GAA technology. The signoff fidelity of our Ansys multiphysics simulation platform is a testament to our continued collaboration with Samsung Foundry at the forefront. Ansys remains committed to providing the best design experience for our mutually advanced customers.”
  • CadenceTom Beckley, Senior Vice President and General Manager, Custom IC & PCB Group at Cadence
    “We congratulate Samsung on this milestone in 3nm GAA production. Cadence worked closely with Samsung Foundry to enable customers to achieve optimal power, performance and area for this node using our digital solutions, from library characterization to full digital flow implementation and sign-off, all powered by our Cadence Cerebrus AI-based technology to maximize productivity. With our custom solutions, we partnered with Samsung to enable and validate a full AMS flow to improve productivity from circuit design and simulation to automated layout. We look forward to continuing this partnership to achieve more tape-out success.”
  • Siemens EDAJoe Sawicki, Executive Vice President for the IC-EDA segment of Siemens Digital Industries Software
    “Siemens EDA is pleased to partner with Samsung to ensure that our existing software platforms will also work on Samsung’s new 3-nanometer process node since the initial development phase. Our long-standing partnership with Samsung through the SAFE™ program generates significant value for our mutual customers by certifying Siemens’ leading EDA tools at 3nm.”
  • SynopsysShankar Krishnamoorthy, General Manager and Corporate Staff for the Silicon Realization Group at Synopsys
    “Through our long-standing strategic partnership with Samsung Foundry, we enable our solutions to support Samsung’s advanced processes, enabling our mutual customers to significantly accelerate their design cycles. Our support for Samsung’s 3nm process with GAA architecture continues to expand, now with our Synopsys Digital Design, Analog Design and IP products, enabling customers to provide differentiated SoCs for key high-performance computing applications.”
1 For more information on Design Technology Co-Optimization (DTCO), see the links below:
Find the optimal for the best. Part 1
Find the optimal for the best. Part 2

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