IISc develops design framework to build next-generation analog chipsets for AI applications

Researchers at the Indian Institute of Science (IISc) have developed a design framework to build next-generation analog computer chipsets that could be faster and require less power than the digital chips found in most electronic devices.

Using their new design framework, the researchers built a prototype of an analog chipset called ARYABHAT-1 (Analog Reconfigurable technology And Bias-scalable Hardware for AI Tasks). This type of chipset can be especially useful for artificial intelligence-based applications such as object or speech recognition – such as Alexa or Siri – or those that require massive parallel computing at high speeds.

Chetan Singh Thakur, assistant professor in the Department of Electronic Systems Engineering (DESE), IISc, whose lab is leading the effort to develop the analog chipset, said: “Most electronic devices, especially those with computers, use digital chips because the design process is simple and scalable. But the advantage of analog is enormous. You get orders of magnitude improvement in power and magnitude. In applications that do not require precise calculations, analog computing has the potential to outperform digital computing because it first is more energy efficient.”

The researchers also said there are several technological hurdles to overcome when designing analog chips. Unlike digital chips, testing and co-designing analog processors is difficult. Large-scale digital processors can be easily synthesized by compiling high-level code, and the same design can be ported across generations of technology development — for example, from a 7nm chipset to a 3nm chipset — with minimal modification, the researchers said.

The researchers added that because analog chips are not easily scalable — they must be individually adapted when transitioning to the next-generation technology or to a new application — their design is expensive. “Another challenge is that it’s not easy to alternate precision and speed with power and space when it comes to analog design. In digital design, simply adding more components such as logic units to the same chip can increase precision, and adjust the power at which they operate without impacting device performance,” a statement from IISc said.

“To address these challenges, the team designed a new framework that will enable the development of analog processors that scale just as much as digital processors. Their chipset can be reconfigured and programmed so that the same analog modules can be carried over to different generations of process design and across different applications. You can synthesize the same kind of chip at 180nm or at 7nm, just like in digital design,” Thakur added.

Several machine learning architectures can be programmed on ARYABHAT and, like digital processors, can operate robustly over a wide temperature range, the researchers said.

They add that the architecture is also “bias-scalable” – performance remains the same when operating conditions such as voltage or current are changed. This means that the same chipset can be configured for ultra-energy-efficient Internet of Things (IoT) applications or for high-speed tasks such as object detection, according to IISc.

The design framework was developed as part of the PhD work of IISc student Pratik Kumar and in collaboration with Shantanu Chakrabartty, professor at the McKelvey School of Engineering, Washington University in St. Louis (WashU), USA, who also serves as WashU’s McDonnell Academy Ambassador to IISc. “It’s good to see the theory of analog bias-scalable computing manifest in reality and for practical applications,” said Chakrabartty, who had previously proposed bias-scalable analog circuitry.

The researchers have also filed for patents and plan to work with industry partners to commercialize the technology.

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