IISc researchers develop design framework for next-generation analog chipsets

This type of chipset is useful for artificial intelligence-based applications such as object or speech recognition, such as Alexa or Siri

This type of chipset is useful for applications based on artificial intelligence, such as object or speech recognition, such as Alexa or Siri

Researchers at the Indian Institute of Science (IISc) have developed a design framework to build next-generation analog computer chipsets that could be faster and require less power than the digital chips found in most electronic devices.

Using a new design framework, the team built a prototype of an analog chipset called ARYABHAT-1 (Analog Reconfigurable technologY And Bias-scalable Hardware for AI Tasks). This type of chipset can be especially useful for artificial intelligence (AI) based applications such as object or speech recognition, such as Alexa or Siri — or those that require massively parallel computing at high speeds, according to an IISc release.

Most electronic devices use digital chips because the design process is simple and scalable. “But the advantage of analog is enormous. You get an order of magnitude improvement in power and size,” explains Chetan Singh Thakur, assistant professor in the Department of Electronic Systems Engineering (DESE), IISc, whose lab is leading the effort to develop the analog chipset. In applications that do not require precise calculations, analog computing has the potential to outperform digital computing because the former is more energy efficient.

But there are technological hurdles; unlike digital chips, testing and co-designing analog processors is difficult. Since analog chips are not easily scalable, they must be individually adapted when transitioning to the next generation of technology or to a new application, and their design is expensive. Another challenge is that trading precision and speed with power and space isn’t easy when it comes to analog design, the release explained.

“To address these challenges, the team designed a new framework that will enable the development of analog processors that scale just as much as digital processors. Their chipset can be reconfigured and programmed so that the same analog modules can be ported across different generations of process design and across different applications,” it said.

The release added that various machine learning architectures can be programmed on ARYABHAT and, like digital processors, can run robustly over a wide temperature range. The researchers also say the architecture is “bias-scalable” — performance remains the same when operating conditions such as voltage or current are changed.

The design framework was developed as part of the PhD work of IISc student Pratik Kumar and in collaboration with Shantanu Chakrabartty, professor at the McKelvey School of Engineering, Washington University in St. Louis (WashU), USA, who also serves as WashU’s McDonnell Academy Ambassador for IISc. The researchers set out their findings in two pre-print studies that are currently under peer review. They also have patents pending and plan to work with industry partners to commercialize the technology, the release said.

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