Indian Institute of Science (IISc)
Researchers at the Indian Institute of Science (IISc) have developed a design framework to build next-generation analog computer chipsets that could be faster and require less power than the digital chips found in most electronic devices. Using their new design framework, the team has built a prototype of an analog chipset called ARYABHAT-1 (Analog Reconfigurable Technology And Bias-scalable Hardware for AI Tasks), the Bengaluru-based IISc said in a statement on Tuesday.
“This type of chipset could be especially useful for artificial intelligence (AI)-based applications such as object or speech recognition — think Alexa or Siri — or those that require massively parallel computing at high speeds,” it said.
Most electronic devices, especially those involving computing, use digital chips because the design process is simple and scalable, it noted.
“But the advantage of analog is enormous. You get an order of magnitude improvement in power and size,” explains Chetan Singh Thakur, assistant professor in the Department of Electronic Systems Engineering (DESE), IISc, whose lab is leading the effort to develop the analog chipset.
In applications that do not require precise calculations, analog computing has the potential to outperform digital computing because the former is more energy efficient. However, there are several technological hurdles to overcome when designing analog chips. Unlike digital chips, testing and co-designing analog processors is difficult.
Large-scale digital processors can be easily synthesized by compiling high-level code, and the same design can be ported to several generations of technology development — for example, from a 7nm chipset to a 3nm chipset — with minimal modification, the statement said.
Because analog chips cannot be easily scaled, they must be individually adapted as they transition to the next generation of technology or to a new application — their design is expensive, it said. Another challenge is that it’s not easy to alternate precision and speed with power and space when it comes to analog design, it added.
In digital design, simply adding more components such as logic units to the same chip can increase precision, and adjust the power they operate at without affecting device performance, the statement said.
To address these challenges, the team designed a new framework that allows for the development of analog processors that scale just as much as digital processors. The chipset can be reconfigured and programmed so that the same analog modules can be ported across different generations of process design and across different applications, it said.
“You can synthesize the same kind of chip at 180nm or at 7nm, just like in digital design,” said Mr. Thakur.
Several machine learning architectures can be programmed on ARYABHAT and, like digital processors, can operate robustly over a wide temperature range, the researchers said. They added that the architecture is also “bias-scalable” — performance remains the same when operating conditions such as voltage or current are changed. This means that the same chipset can be configured for ultra-energy efficient Internet of Things (IoT) applications or for fast tasks such as object detection.
The design framework was developed as part of the PhD work of IISc student Pratik Kumar and in collaboration with Shantanu Chakrabartty, professor at the McKelvey School of Engineering, Washington University in St. Louis (WashU), USA, who also serves as WashU’s McDonnell Academy Ambassador for IISc.
“It’s good to see the theory of analog bias-scalable computing manifested in reality and for practical applications,” said Mr Chakrabartty, who had previously proposed bias-scalable analog circuitry. The researchers set out their findings in two pre-print studies that are currently under peer review. They also have patents pending and plan to work with industry partners to commercialize the technology, the statement said.
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