Researchers Develop Design Framework to Build Next-Generation Analog Computing Chipsets.

Design framework for building next-generation analog computer chipsets

IISc Researchers have created a design framework for creating next-generation analog computer chipsets, which may run faster and with less power than the digital chips used in most electronic devices.

Researchers develop design framework to build next-generation analog computer chipsets
ARYABHAT-1 Chip Micrograph. Image Credit: NeuRonICS Lab, DESE, Indian Institute of Science.

The group has prototyped an analog chipset called ARYABHAT-1 (Analog Reconfigurable technology And Bias-scalable Hardware for AI Tasks) using their innovative design framework. This kind of chipset could be particularly useful for applications based on artificial intelligence (AI), such as object or speech recognition, such as Alexa or Siri, or applications that require highly efficient massively parallel computations.

Digital chips are used in most electronic devices, especially those involving computing, because the design process is simple and scalable.

But the advantage of analog is enormous. You will get orders of magnitude improvement in strength and size

Chetan Singh Thakur, Assistant Professor, Department of Electronic Systems Engineering (DESE), Indian Institute of Science

The development of the analog chipset is led by Chetan Singh Thakur’s lab. Analog computing has the potential to outperform digital computing in applications that do not require precise calculations because the former is more energy efficient.

When designing analog chips, there are several technological challenges that must be overcome. Analog processor testing and co-design are challenging, unlike digital chips. Compiling high-level code makes it easy to create large-scale digital processors, and the same design can be transferred between generations of technology development with little modification, such as from a 7nm chipset to a 3nm chipset.

The design of analog chips is costly because they are difficult to scale and require individual adjustments as they transition to new applications or next-generation technology. Another problem with analog design is that it’s difficult to trade power and space for accuracy and speed.

In digital design, precision can be increased by simply adding more logic units to the same chip, and the power at which they function can be changed without affecting the functionality of the device.

The team has created a new framework that allows the creation of analog processors similar to digital processors to overcome these problems. Their chipset can be modified and programmed so that the same analog modules can be used in different applications and generations of process design.

You can synthesize the same kind of chip at 180nm or at 7nm, just like digital design

Chetan Singh Thakur, Assistant Professor, Department of Electronic Systems Engineering (DESE), Indian Institute of Science

The researchers claim that ARYABHAT can be used to program various machine learning architectures that, like digital processors, can function reliably over a wide temperature range. They go further by stating that the architecture is also “bias-scalable”, meaning that even when operating conditions, such as voltage or current, change, performance does not change.

This means that the same chipset can be set up for both fast tasks such as object detection and Internet of Things (IoT) applications that require extremely low power consumption.

The design framework was created by Pratik Kumar, a Ph.D. student at IISc, in partnership with Shantanu Chakrabartty, a professor at Washington University in St. Louis’ (WashU) McKelvey School of Engineering and WashU’s McDonnell Academy Ambassador to IISc.

It is good to see the theory of analog bias scalable computing manifesting itself in reality and for practical applications.

Shantanu Chakrabartty, professor, Washington University in St. Louis

Chakrabartty had previously proposed bias-scalable analog circuits.

Two pre-print studies undergoing peer review present the researchers’ findings. In addition, they have filed for patents and plan to work with business partners to commercialize the technology.

Source: https://iisc.ac.in/

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